This application claims the benefit of Korean Application No. P2001-71572 filed in Korea on Nov. 17, 2001, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile memory device and a driving method thereof.
2. Discussion of the Related Art
Generally, a nonvolatile ferroelectric memory device, for example FRAM (Ferroelectric Random Access Memory), has a data processing speed similar to that of DRAM (Dynamic Random Access Memory), and also enables retention of stored data when power is off, thereby attracting public interest as a next generation memory device.
FRAM is a memory device having a structure similar to DRAM. However, unlike a DRAM memory cell, an FRAM memory cell uses ferroelectrics as a capacitor material to benefit from a high remanent polarization characteristic of ferroelectric materials. Due to the remanent polarization of the ferroelectric capacitor, data stored in an FRAM memory cell is not erased even if the electric field applied across the memory cell is removed.
FIG. 1 illustrates a graph of a hysteresis loop typical of ferroelectrics. Referring to FIG. 1, polarization induced by an electric field is not eliminated even if the electric field is removed, but maintains a predetermined quantity (d or a state) due to remanent polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is a memory device using the d and a states of the ferroelectric capacitive material therein as digital logic value xe2x80x9c1xe2x80x9d and digital logic value xe2x80x9c0xe2x80x9d, respectively.
A nonvolatile ferroelectric memory device according to a related art is explained in the following by referring to the attached drawings. FIG. 2 illustrates a diagram of a unit cell of a general ferroelectric memory. Referring to FIG. 2, a bit line B/L is disposed in one direction of the memory device; a word line W/L is disposed in a transversal direction with respect to the bit line B/L; a plate line P/L is disposed in the same direction as the word line W/L and at a predetermined distance therefrom; a transistor T1 is disposed in such a manner that a gate and a source thereof are respectively connected to the word and bit lines, and a ferroelectric capacitor FC1 is disposed in such a manner that the first and second terminals thereof are respectively connected to the drain of transistor T1 and the plate line P/L of the memory device.
Data input/output operation of such a nonvolatile ferroelectric memory device is explained as follows. FIG. 3A illustrates a timing diagram for a plurality of signals at the input and output lines of a ferroelectric memory device during a write operation. The write operation is initiated by activating a chip enable signal CSBpad at an input of the memory cell using a high to low transition of an externally applied electrical signal, and simultaneously activating a write enable signal WEBpad with a high to low transition. Subsequently, during an address decoding stage of the write operation, a pulse applied to the word line of a cell is driven low to high to select that cell. To complete the write operation, a high or low signal is applied to the plate line corresponding to the selected memory cell for a predetermined time interval while the word line is asserted. Furthermore, a high or low signal synchronized with the write enable signal WEBpad is applied to the corresponding bit line depending on whether the input data to be written to the selected FRAM cell is digital logic value xe2x80x9c1xe2x80x9d or digital logic value xe2x80x9c0xe2x80x9d. Specifically, if the plate line is driven by a low signal while the word line is asserted and the bit line is high, then digital logic value xe2x80x9c1xe2x80x9d is recorded in the ferroelectric capacitor of the memory cell. If the plate line is driven by a high signal and the bit line is low, then digital logic value xe2x80x9c0xe2x80x9d is recorded in the ferroelectric capacitor.
FIG. 3B illustrates a timing diagram for a plurality of signals at the input and output lines of a ferroelectric memory device during a read operation. The read operation for extracting stored data from the ferroelectric cell is explained as follows. When the chip enable signal CSBpad is asserted with a high to low voltage externally applied, all the bit lines are held at a low voltage by a driving signal before the corresponding word line is selected. After the bit lines have been deactivated, address decoding is performed. Then, the signal applied to the corresponding word line is raised from a low to a high level by an address decoder to select the targeted cell. A high level signal is applied to the plate line of the selected cell. Consequently, if digital logic value xe2x80x9c1xe2x80x9d was stored in the FRAM cell, the ferroelectric capacitor will be switched from the corresponding polarization state Qs to the opposite polarization state, thereby destroying the data stored in the memory cell. In contrast, if the data stored in the ferroelectric memory cell is digital logic value xe2x80x9c0xe2x80x9d, then the polarization state Qns of the capacitor is not switched by the signal applied to the plate line.
The variation of electric charge between the electrical dipoles in the ferroelectric material will differ depending on whether the polarization state of the cell is switched or not. Hence, the variation of the polarization state from a digital logic value xe2x80x9c1xe2x80x9d to digital logic value xe2x80x9c0xe2x80x9d can be detected using a sense amplifier. Specifically, when data stored in the memory cell is destroyed by a read operation, the polarization state changes from d to f according to the hysteresis loop in FIG. 1. In contrast, when stored data is not destroyed by the read operation, the polarization state is changed from a to f. A sense amplifier is ordinarily used to differentiate between the two state transitions. When enabled for a specific time duration, the sense amplifier outputs digital logic value xe2x80x9c1xe2x80x9d if the data stored in the memory cell is erased. However, when the data is not erased, the resulting amplification keeps the output at digital logic value xe2x80x9c0xe2x80x9d. Hence, the original data can be restored using the output of the sense amplifier. Accordingly, the plate line is deactivated xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d while the high signal is applied to the corresponding word line.
In a schematic diagram of a nonvolatile ferroelectric memory device in FIG. 4 according to the related art, a cell array unit has a folded bit line structure and one sense amplifier is shared by every two main bit lines in the cell array unit, and a middle reference array unit is formed between the cell array unit and an adjacent cell unit array (not shown in the drawing).
A detailed structure of the above-explained nonvolatile ferroelectric memory device is depicted in FIG. 5. The memory device comprises a top section consisting of a first and second cell array units, and a bottom section consisting of a third and fourth array units. The top and bottom sections of the memory device are symmetrically disposed above and below a row of sense amplifiers, respectively. Moreover, an upper reference array unit is disposed between the first and second array units, and a lower reference array unit is disposed between the third and fourth array units.
Each of the cell array units has a folded bit line structure. The two bit lines in the top section shares a corresponding sense amplifier through a first control signal A, and the other two bit lines in the bottom section share the sense amplifier through a second control signal B.
Specifically, if a first bit line in the top section is used as a main bit line, a second adjacent bit line in the top section is used as a reference bit line. Moreover, if a first bit line in the bottom section is used as a main bit line, a second adjacent bit line in the bottom section is used as a reference bit line. Switching transistors are formed between the bit lines and the corresponding sense amplifiers to be controlled by the first and second control signals, respectively. Each of the sense amplifiers, as shown in FIG. 6, has the structure of a latch type amplifier in which bit line signal BL and conjugate bit line signal/BL are connected to both output nodes of the sense amplifier.
Unfortunately, the nonvolatile ferroelectric memory device according to the related art has the following problem or disadvantage. Since adjacent bit lines are used as the main and reference bit lines in the folded bit line structure, the reference data fluctuates randomly due to a capacitive coupling noise component of the main data. Hence, a sensing margin is reduced by the effects of this coupling noise.
Accordingly, the present invention is directed to a nonvolatile ferroelectric memory device and a driving method thereof that substantially obviate one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a nonvolatile ferroelectric memory device and a driving method thereof suitable for increasing a sensing margin by overcoming the problem caused by the coupling noise of the bit lines.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will become apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described, the nonvolatile ferroelectric memory device includes a plurality of sense amplifiers, a top cell array unit disposed at an upper section, and a bottom cell array unit disposed at a lower section, the top and bottom cell array units each including a plurality of unit cells, and the top and bottom cell array units being disposed symmetrically about the sense amplifiers, at least one top reference array unit in a vicinity of the top cell array unit, and at least one bottom reference array unit in a vicinity of the bottom cell array unit, a plurality of main bit lines connected to the unit cells of the top or bottom cell array unit, and a plurality of reference bit lines of the bottom or top cell array unit, wherein reference bit lines of the bottom cell array unit correspond to main bit lines of the top cell array unit disposed symmetrically about the sense amplifiers, and reference bit lines of the top cell array unit correspond to main bit lines of the bottom cell array unit disposed symmetrically about the sense amplifiers.
In another aspect of the present invention, the nonvolatile ferroelectric memory device includes a top cell array unit including a plurality of unit cells, a bottom cell array unit including a plurality of unit cells, a middle reference array unit disposed in a middle area between the top and bottom cell array units, a plurality of edge reference array units disposed at edge sections of the top and bottom cell array units, respectively, and a plurality of sense amplifiers, wherein the top cell array unit is disposed at an upper section, the bottom cell array unit is disposed at a lower section, the top and bottom cell array units being disposed symmetrically about the sense amplifiers, wherein the sense amplifiers are disposed alternately to lie each between the top and bottom cell array units, or between the top cell array unit and an edge reference array unit, or between the bottom cell array unit and an edge reference array unit, wherein bit lines at the lower section below the sense amplifiers disposed between the top and bottom cell array units and the edge reference array units are main bit lines when the bit lines at the upper section above the sense amplifiers disposed between the top and bottom cell array units and the edge reference array units are reference bit lines, and wherein the bit lines at the lower section below the sense amplifiers formed between the top and bottom cell array units and the edge reference array units are the reference bit lines when the bit lines at the upper section above the sense amplifiers formed between the top and bottom cell array units and the edge reference array units are the main bit lines.
In another aspect of the present invention, the nonvolatile ferroelectric memory device includes top and bottom cell array units disposed at an upper and a lower sections symmetrical about a plurality of sense amplifiers, each cell array unit including a plurality of unit cells, a plurality of reference array units disposed at edge sections of the top and bottom cell array units corresponding to the sense amplifiers, respectively, a plurality of bit lines wherein two of the bit lines of the top cell array unit and two of the corresponding bit lines of the bottom cell array unit share one of the sense amplifiers, wherein the bit lines at the lower area symmetrical about the sense amplifiers are used as reference bit lines when the bit lines at the upper area symmetrical about the sense amplifiers are used as main bit lines, and wherein two bit lines adjacent to the main and reference bit lines at the upper and lower sections are used as dummy reference bit lines, and a plurality of switching devices receiving first and second control signals to control whether to connect the sense amplifiers and bit lines to each other wherein corresponding bit lines from the upper and lower sections are symmetrical about the sense amplifiers and are controlled by the same control signal.
In another aspect of the present invention, in a nonvolatile ferroelectric memory device that includes top and bottom cell array units disposed at upper and lower sections symmetrical about sense amplifiers to include a plurality of unit cells, respectively, at least one reference array unit disposed in a vicinity of each of the top and bottom cell array units to correspond to each other, and bit lines disposed on the upper and lower sections to share the sense amplifiers, respectively, a method of driving the nonvolatile ferroelectric memory device having the feature that a reference voltage generated from the reference array unit is applied to the bit lines disposed at the lower sections below the sense amplifiers so that the bit lines at the lower sections operate as reference bit lines when the bit lines disposed at the upper sections above the sense amplifiers operate as main bit lines.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.